The present invention relates to a semiconductor storage device having a capacitor and a MOS transistor, and more particularly, to a semiconductor storage device whose capacitor has a dielectric film formed of a ferroelectric substance or a high dielectric substance.
At present, DRAMs (Dynamic Random Access Memories) each constructed of one MOS (Metal Oxide Semiconductor) transistor and one capacitor are mainly manufactured. With demands for high integration and fine processability in recent years, it has become more and more difficult to secure the cell capacity in the DRAMs having such a construction. Therefore, generally, efforts are made to develop methods of increasing the area of an electrode to secure the cell capacity. More specifically, the area of the electrode is increased by constructing the electrode in a three-dimensional structure. However, because this method causes the manufacturing process to be very complicated, attempts to increase the area of the electrode by this method have almost reached the limit. Further, thinning of the dielectric itself has almost reached the limit. Therefore, in order to secure the cell capacity, researches are being made to develop new methods of using an oxide having a high dielectric constant (hereinafter referred to as "high dielectric") such as SrTiO.sub.3 or (Ba, Sr)TiO.sub.3 as a dielectric material.
In the meantime, with the progress of a thin film forming technique, ferroelectric non-volatile memories (FeRAM) operating at a high density and at a high speed are being developed by combining the thin film technique and a semiconductor memory fabricating technique with each other. The researches of such ferroelectric non-volatile memories are energetically made for practical application because it is considered that due to their properties of high-speed write/read, operations at low voltages, and a high resistance to repeated write/read operations, the ferroelectric non-volatile memories will be able to replace not only the conventional non-volatile memories such as EPROMs (Erasable Programmable ROMs), EEPROMs (Electrically Erasable and Programmable ROMs), and flash memories, but also SRAMs (static RAMs) and DRAMs (Dynamic RAMs).
For ferroelectric materials, the following substances have been investigated: PbZrTiO.sub.3 (hereinafter referred to as "PZT"), and SrBi.sub.2 Ta.sub.2 O.sub.9 and Bi.sub.4 Ti.sub.3 O.sub.12 which each have fatigue characteristics more favorable than the PZT and can be driven at low voltages. However, in order to allow these ferroelectrics and the high dielectrics to display their characteristics fully, it is necessary to heat-treat them in an ambient of oxidizing gas at a temperature of as high as 400.degree. C.-800.degree. C.
When forming highly integrated DRAMs or FeRAMs having a stack construction by using the ferroelectric or high dielectric material of the above-described kind, a plug formed of polysilicon (i.e., polycrystalline silicon) or the like is typically used to electrically connect a MOS section and a capacitor section with each other. FIG. 2 shows a cross-sectional view of a conventional semiconductor storage device having such a construction.
In FIG. 2, reference numeral 21 denotes a silicon substrate, reference numeral 22 denotes a gate electrode, reference numerals 23 and 24 denote a source region and a drain region, respectively, reference numeral 25 denotes a polysilicon plug, reference numeral 26 denotes a LOCOS (LOCal Oxidation of Silicon) oxide film, and reference numerals 27 and 31 denote interlaminar insulation films. Also, reference numerals 29, 30, and 32 respectively denote a lower electrode, a ferroelectric film, and an upper electrode of a capacitor section, and reference numeral 33 denotes a bit line.
The lower electrode 29 is formed of platinum (Pt), which material displays a high degree of resistance to oxidation during the film forming process at a high temperature. The barrier metal 28 is provided between the lower electrode 29 and the plug 25. The provision of the barrier metal 28 is necessary because the barrier metal 28 prevents Pt of the lower electrode 29 from reacting with silicon of the plug 5 and also prevents elements composing the ferroelectric film 30 (or a high dielectric film) from diffusing through the lower electrode 29 to other films during a heat-treating process. For the material of the barrier metal 28, TiN, for example, is known.
However, if the barrier metal is formed of TiN, TiN in the barrier metal is easily oxidized by oxygen included in an atmosphere and permeating through Pt of the lower electrode during the heat-treatment of the ferroelectric or high dielectric. Consequently, a volume change and a film stress occur, which results in separation of TiN of the barrier metal from Pt of the lower electrode and which will cause hillocks and cracks in Pt of the lower electrode. On the other hand, if SrBi.sub.2 Ta.sub.2 O.sub.12 (SBT), which has a very good fatigue characteristic as compared with PZT, is used for a non-volatile memory, it is impossible to employ a combination of Pt and TiN because SBT requires a heat treatment at a higher temperature (700.degree. C.) than PZT does.
It is also known to use PtRh in place of Pt as the lower electrode material (see JP-A-9-45872). This PtRh, however, does not sufficiently function as a barrier to oxygen, either.